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HV623 32-Channel 128-Level Amplitude Gray-Shade Display Column Driver
Ordering Information
Package Option Device HV623 64-Lead 3-sided Plastic Gullwing HV623PG
Features
5V CMOS inputs Up to 80V modulation voltage Capable of 128 levels of gray shading 20MHz data throughput rate 32 outputs per device (can be cascaded) Pin-programmable shift direction (DIR) D/A conversion cycle time is 32s Diodes in output structure allow usage in energy recovery systems Integrated HVCMOS(R) technology Available in 3-sided 64-lead gullwing package
General Description
The HV623 is a 32-channel driver IC for gray shade display use. It is designed to produce varying output voltages between 3 and 80 volts. This amplitude modulation at the output is facilitated by an external ramp voltage VR. See Theory of Operation for detailed explanation. This device consists of a dual 16-bit shift registers, 32 data latches and comparators, and control logic to preform 128 levels of gray shading. There are 7 bits of data inputs. Data is shifted through the shift registers at both edges of the clock, resulting a data transfer rate of twice of the shift clock frequency. When the DIR pin is high, CSI/CSO is the input/output for the chip select pulse. When DIR is low, CSI/CSO is the output/input for the chip select pulse. The DIR = HIGH also allows the HV623 to shift data in the counterclockwise direction when viewed from the top of the package. When the DIR pin is low, data is shifted in the clockwise direction. The output circuitry allows the energy which is stored in the output capacitance to be returned to VPP through the body diode of the output transistor.
Absolute Maximum Ratings
Supply voltage, VDD1 Supply voltage, Logic input VPP1 levels1 -0.5V to +7.5V -0.5V to +90V -0.5 to VDD + 0.5V 1.5A 1W -40C to +70C -65C to +150C 260C
Ground current 2 Continuous total power dissipation3 Operating temperature range Storage temperature range Lead temperature 1.6mm (1/16 inch) from case for 10 seconds
Notes: 1. All voltages are referenced to GND. 2. Duty cycle is limited by the total power dissipated in the package. 3. For operation above 25C ambient derate linearly to 70C at 22.2mW/C.
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HV623
Electrical Characteristics (at TA = 25C, over operating conditions unless otherwise specified)
Low-Voltage DC Characteristics (Digital)
Symbol IDD IDDQ IIH IIL CIN2 IOH IOL Parameter VDD supply current Quiescent VDD supply current High-level input current Low-level input current Input capacitance (data, LC, SC, CC) High-level output current Low-level output current -2 2 1.0 -1.0 Min Typ1 12 Max 20 100 50 -50 15 Units mA A A A pF mA mA Conditions fSC = 10MHz fCC = 8MHz All VIN = 0V, VDD = max VIH = VDD VIL = 0V VIN = 0V, f = 1MHz VDD = 4.5V VDD = 4.5V
Notes 1. All typical values are at VDD = 5.0V. 2. Guaranteed by design.
Low-Voltage DC Characteristics (Analog)
Symbol IDD IDDQ Parameter VDD supply current Quiescent VDD supply current Min Typ Max 100 100 Units A A Conditions fSC =10MHz fCC = 8MHz All VIN = 0V, VDD = max
High-Voltage Bias Circuit for Output Variation Control
Symbol IPP Parameter VPP supply current for bias circuit Min Typ 2 Max Units mA Conditions Depending on external bias circuit, see Table 1.
High-Voltage DC Characteristics
Symbol IAOH IAOL VO Parameter High-voltage analog output source current High-voltage analog output sink current Maximum delta voltage between high voltage outputs of the same level Min Typ Max Units mA mA V Conditions VPP = 80V See test circuit VPP = 80V, VDD = 4.5V VAO = 2V At all gray levels See Performance Curves See Performance Curves 0.2
Recommended Operating Conditions
Symbol VDD VDD VIH VIL VBIAS VCTL VPP VR fSC TA Parameter Low-voltage digital supply voltage Low-voltage analog supply voltage High-level input voltage (analog and digital) Low-level input voltage (analog and digital) IPP control circuit bias voltage IPP control circuit control voltage High-voltage supply Ramp voltage Shift clock operating frequency (at VDD = 5.5V) Operating free-air temperature -40 -0.3 0 Min 4.5 4.5 VDD -1 0 -2 0 0 2 80 VPP -2 10.2 70 Typ 5.0 5.0 Max 5.5 5.5 VDD 1 Units V V V V V V V V MHz C
Notes: Power-up sequence should be the following: 1. Connect ground. 2. Apply VDD. 3. Set all inputs (Data, CLK, Enable, etc.) to a known state. Power-down sequence should be the reverse of the above.
4. Apply VPP.
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HV623
Electrical Characteristics
AC Characteristics (VDD = 5.5V, TA = 25C) Logic Timing
Symbol fSC fDIN tSS tHS tWA tDS tDH tWD tWLC tDLCR tDRCC1 tDSL tCSC tWSC tCCC tWCC Parameter Shift clock operating frequency Data-in frequency CSI/CSO pulse to shift clock setup time CSI/CSO pulse to shift clock hold time CSI pulse width Data to shift clock setup time Data to shift clock hold time Data-in pulse width Load count pulse width Load count to ramp delay Ramp to count clock delay Shift clock to load count delay time Shift clock cycle time Shift clock pulse width Count clock cycle time Count clock pulse width 98 49 98 49 1 0.47 98 40 0 49 20 0 24 98 Min Typ Max 10.2 20.4 Units MHz MHz ns ns ns ns ns ns ns s s ns ns ns ns ns Conditions
Note 1: Count clock starts counting after 0.47s min. This is equivalent to a time duration for a linear ramp VR to ramp from 0 to 3V, assuming the minimum value of TRR, ramp size time of 12s for VR = 80V.
VRAMP Timing
Symbol tCR tRR tHR2 tFR Parameter Cycle time of ramp signal Ramp rise time Ramp hold time Ramp fall time Min 15 12 2 TBD 15 3 Typ Max Units s s s s Conditions
Note 2: The maximum ramp hold time may be longer than 15 s, but the output voltage HVOUT will droop due to leakage.
Table 1:
Schemes to control IPP bias current, typical IPP
Option 1 VBIAS (V) 0 0 VCTL (V) 0.1 1.0 RCTL () 56K 56K IPP (mA) 2 7 Option 2 VBIAS (V) -1.0 -2.0 VCTL (V) 0 0 RCTL () 56K 56K IPP (mA) 4 5.5
+ -
VCTL HV623 VCTL
+ -
RCTL RCTL VBIAS
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HV623
Pin Definitions
Pin # 30-36 26 22 43 40 Name D1-D7 SC (Shift Clock) CSI (Chip Select Input) CSO (Chip Select Output) LC (Load Count) Function Inputs for binary-format parallel data. Triggers data on both rising and falling edges. This implies that the data rate is always twice the clock rate (data rate = 20MHz max if clock rate = 10MHz max). Input pin for the chip select pulse (when DIR is high). Output pin for the chip select pulse (when DIR is low). Input pin for the chip select pulse (when DIR is low). Output pin for the chip select pulse (when DIR is high). Input for a pulse whose rising edge causes data from the input latches to enter the comparator latches, and whose falling edge initiates the conversion of this binary data to an output level (D-to-A). Also, the HVOUT will clear to zero after the load count is initiated. High-voltage ramp input for charging the output stage hold capacitors (CH). This input can be linear or non-linear as desired. When this pin is connected to VDD, input data is shifted in ascending order, i.e., corresponding to HVOUT1 to HVOUT32. When connected to LVGND, input data is shifted in descending order, i.e., corresponding to HVOUT32 to HVOUT1. This is ground for the logic section. HVGND and LVGND should be connected together externally. This is ground for the high-voltage (output) section. HVGND and LVGND should be connected together externally. This input biases the output source followers. High-voltage outputs. Low-voltage analog supply voltage. Low-voltage digital supply voltage. Voltage supply pin to prevent output voltage from being affected by its adjacent outputs (VCTL = 2V for a particular panel). The combination of VCTL and RCTL will reduce the output voltage variation to less than 0.2V of delta voltage between high voltage outputs of the same level at all gray levels. Current sense resistor to ground to prevent output voltage from being affected by its adjacent outputs (RCTL = 56K for a particular panel). See VCTL function above.
42 18, 47 28
CC (Count Clock) Input to the count clock generator whose increments are compared to the data in the comparator latches. VR DIR
27, 38 17, 48 19, 45 1-16 49-64 21 29 24
LVGND HVGND VPP HVOUT1HVOUT32 VDD (Analog) VDD (Digital) VCTL
25
RCTL
Input and Output Equivalent Circuits
VDD VDD
Input
Data Out
GND (Logic) Logic Inputs
GND (Logic) Logic Data Output
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HV623
Output Stage Detail
VR VPP CH
Test Circuit
High-voltage Analog Output Source Current (IAOH) For gray shade #1 (000 0000)
VR VPP = 80V
HV623 + - 70V
VCTL
Q1 Internal Logic & Bias Circuit Q2
0V
Logic
Output Stage
HVOUT + 1K Vtst
HVOUT
LVGND HVGND
10K
RCTL
1. 2. 3. 4. 5.
Set HVOUT = Low. Apply VPP = 80V. Apply a step voltage of 70V at VR (slew rate = 4.1V/s). Measure voltage across the 1K resistor. V Output source current can be calculated by using tst . 1K
Functional Block Diagram
7 7
See Output Stage Detail GND VR VPP L/E
1 L/E 2 VCTL Dual 16-bit Shift Registers
Data Latches Data Latches
Latches and Comparators Latches and Comparators
RS F/F RS F/F
Output Stage Output Stage
HVOUT 1
7
7
HVOUT 2
RCTL
L/E 31 L/E 32
Data Latches Data Latches
7
Count
Load
Latches and Comparators
7
RS F/F RS F/F Clear
Output Stage Output Stage
HVOUT 31
7
Latches and 7 Comparators
HVOUT 32
7 SC SC DIR Shift Clock Buffer Data In Buffers Clear Pulse Generator Count Load I/O Buffers I/O Buffers
Counter Reset Counter Load Count Buffer
CC
Count Clock Buffer
CSI
CSO
SC
D7
D1
LC
CC
SC = Shift Clock LC = Load Count CC = Count Clock
CSI = Chip Select Input CSO = Chip Select Output *Strobe = twice the SC frequency
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HV623
Typical Panel Connections
Data Bus (7) DIR = LOW VR, VPP LVGND, HVGND, SC, LC, CC, CSO
32
1
32
1
32
1
Display Panel (Example)
VR, VPP LVGND, HVGND, SC, LC, CC, CSI DIR = HIGH Data Bus (7)
1
32
1
32
1
32
Gray Shade Decoding Scheme
Shade Number 128 127 126 125 124 123 122 121 D7 1 1 1 1 1 1 1 1 D6 1 1 1 1 1 1 1 1 D5 1 1 1 1 1 1 1 1 D4 1 1 1 1 1 1 1 1 D3 1 1 1 1 0 0 0 0 D2 1 1 0 0 1 1 0 0 D1 1 0 1 0 1 0 1 0
Gray Scale Voltage
(000 0000)
VR HVOUT HVOUT HVOUT
Gray Scale Voltage
HVOUT
(111 1111) 01 2 *** Clock Cycle 127
HVOUT
7 6 5 4 3 2 1
0 0 0 0 0 0 0
0 0 0 0 0 0 0
0 0 0 0 0 0 0
0 0 0 0 0 0 0
1 1 1 0 0 0 0
1 0 0 1 1 0 0
0 1 0 1 0 1 0 12-127
HV623
Function Table
Sequence Function DIR Data-In (D1 - D7) H L H L X X X Pre-define by 1 or 2 L L L Output CSI CSO Shift Clock Load Count L L L Count Clock L L L L VR HVOUT
1 2 3 4 5
Shift Data from HVOUT1 to 32 Shift Data from HVOUT32 to 1 Load Shift Register Load Counter Counting/Voltage Conversion
H L X X X
Output
L L L L Initiates VRAMP
L H L H -
Timing Diagrams
(a) Basic System Timing
t CR VR Load First Device t RR t HR t FR
Chip Select Input (CSI) Chip Select Output (CSO) Shift Clock (SC)
Load Second Device
Load Last Device

Data In (D1 - D7)
Data from Data Bus (See Detailed Timing) t DLCR
Load Count* (LC) Count Clock (CC)

1
2
3
4
5
128
1
2
3
4
5
128
HV OUT
*HVOUT will clear to zero with load count.
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HV623
(b) Detailed Device Timing
LOADING LAST DEVICE NEXT LOADING CYCLE
t WA
Chip Select Input (CSI)
t HS t SS
Shift Clock (SC)
SC 1
t CSC
SC 2 SC 16 SC 1 SC 16
Data (D1-D7)
DATA SET 1
DATA SET 2
DATA SET 3
DATA SET 31
DATA SET 32
DATA SET 1
DATA SET 31
t DH t DS
Load Count (LC)
t WD
t DSL t WLC
t WCC t CCC
Count Clock (CC)
Count Clock 1 t DRCC t DLCR
3V 0V
Count Clock 128
80V
VR
Typical Performance Curves
Source Output Characteristics
15 15
Sink Output Characteristics
12
12
IO (milliamperes)
9
IO (milliamperes)
0 1 2 3 4 5 6 7 8
9
6
6
3
3
1
0 0 1 2 3 4 5 6 7 8
VGS Volts
VGS Volts
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HV623
Pin Configuration
64-Pin PG Package Pin Function 1 HVOUT 1 2 HVOUT 2 3 HVOUT 3 4 HVOUT 4 5 HVOUT 5 6 HVOUT 6 7 HVOUT 7 8 HVOUT 8 9 HVOUT 9 10 HVOUT 10 11 HVOUT 11 12 HVOUT 12 13 HVOUT 13 14 HVOUT 14 15 HVOUT 15 16 HVOUT 16 17 HVGND 18 VR 19 VPP 20 N/C 21 VDD (Analog)* 22 CSI Pin 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 Pin Function 45 N/C 46 VCTL 47 RCTL SC (Shift Clock) 48 LVGND 49 DIR 50 VDD (Digital)* 51 D7 52 53 D6 54 D5 55 D4 56 D3 57 D2 58 D1 59 N/C LVGND 60 N/C 61 LC (Load Count) 62 N/C 63 CC (Count Clock) 64 CSO N/C Function VPP N/C VR HVGND HVOUT 17 HVOUT 18 HVOUT 19 HVOUT 20 HVOUT 21 HVOUT 22 HVOUT 23 HVOUT 24 HVOUT 25 HVOUT 26 HVOUT 27 HVOUT 28 HVOUT 29 HVOUT 30 HVOUT 31 HVOUT 32
Package Outlines
1 Index 64
top view
24
41
25
40
3-Sided Plastic QFP 64-pin Gullwing Package
* Analog VDD and digital VDD may be connected separately for better noise immunity.
Theory of Operation
The HV623 has two primary functions: 1) Loading data from the data bus and, 2) Gray-shade conversion (converting latched data to output voltages). Since the device was developed initially for flat panel displays, the operation will be described in terms that pertain to that technology. As shown by the Typical Drive Scheme, several HV623 packages are mounted at the top and bottom of a display panel. Data exists on a 7-bit bus (adjacent PC board traces) at top and bottom. The D1 through D7 inputs of each chip take data from the bus when either a CSI or CSO pulse is present at the chip. These pulses therefore act as a combination CHIP SELECT and LOCATION STROBE. Because of the way the chip HVOUT pins are sequenced, data on the bus at the bottom of the display panel will be entered into the left-most chip as HVOUT1, HVOUT2, etc. up to HVOUT32. The CSI pulse will accomplish this with DIR = High.
Loading Data from Data Bus
Here is the full data-entry sequence: 1) The microcontroller puts data on the bus (7 bits) 2) To enter the data into the 32 sets of 7 latches on the first chip, the shift clock rises. This positive transition is combined with the CSI pulse and is generated only once to strobe the data into the first set of latches. (These latches eventually send data to the HVOUT1). The data on the bus then changes, the shift clock falls, and this negative transition is combined with the CSI pulse, which is now propagated internally, to strobe the new data into the next set of 7 latches (which will end up as HVOUT2). This internal CSI pulse therefore runs at twice the shift clock rate. 3) When the last set of 7 latches in the first chip has been loaded (HVOUT32), the CSI pulse leaves chip 1 and enters chip 2. The exit pin is called CSO and the chip 2 entry pin is CSI . For chips at the top of the panel things are reversed: DIR is low, entry pins are CSO and exit pins are CSI , because the data-into-latches sequence is in descending order, HVOUT32 down to HVOUT1. 4) The buses may of course be separate, and data can be strobed in on an interleaved basis, etc., but those complications will be left to systems designers.
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HV623 When data has been loaded into all 32 outputs of all chips (top and bottom of the display panel), the load count pin is pulsed. On its rising transition, all output levels are reset to zero and all the data in the input latches is transferred to a like number of comparator latches, (thus leaving the data latches ready to receive new data during the following operations). After the transfer, the load count pin is brought low. This transition begins the events that convert the binary data into a gray-shade level.
Output Voltage Variation
The output voltage of the HV623 is determined by the logic and the ramp voltage VR. It is possible that the output voltage may be coupled to an unacceptable level due to its adjacent outputs through the panel. In order to solve this problem, internal logic (refer to Output Stage Detail) is integrated in the IC to minimize the effect. Two external pins VCTL and RCTL allow the feasibility to control the current flowing through Q2. The VCTL pin is connected to a voltage source and the RCTL pin is connected to ground through a resistor (2V and 56K are used for a particular panel). The internal bias circuit will drive the resistor to a voltage level that is equal to the VCTL voltage at steady state through an operational amplifier. The current flowing through Q1 and Q2 will be limited to VCTRL/RCTRL. This combination of VCTL and RCTL will reduce the output voltage variation to less than 0.2V of delta voltage for each gray shade, independent of its adjacent output voltages.
Gray-shade Conversion
1) The COUNT CLOCK is started. An external signal is applied to the COUNT CLOCK pin, causing the counter on each chip to increment from binary 000 0000 to 111 1111 (0 to 127). 2) At the same time, the VR voltage is applied to all chips, via charging transistors, causing the HOLD CAPACITOR (CH) on each output to experience a rise in voltage. 3) The logic control compares the count in the comparator latch to the count clock. The gate voltage of Q1 and the output voltage HVOUT will ramp up at the same rate as VR. 4) Once VR has reached the maximum voltage, then all the pixels will be at the final value. (See Output Gray Scale Voltage.)
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